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Advances in Computer Science and Engineering
Volume 2, Issue 2, Pages 165 - 187 (July 2008)

THE TOTAL SYSTEM RELIABILITIES FOR FAULT-TOLERANT SELF-RECONFIGURABLE ARRAY SYSTEMS Tadayoshi Horita (Japan) and Itsuo Takanami (Japan) Received May 2, 2008 References:
[1] Y. Y. Chen, S. J. Upadhyaya and C. H. Cheng, A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors, IEEE Trans. Comput. 46(12) (1997), 1363-1371. [2] F. Distante, M. G. Sami and R. Stefanelli, Reconfiguration techniques in the presence of faulty interconnections, Proc. Int’l Conference on WSI, 1989, pp. 379-388. [3] T. Horita and I. Takanami, An efficiently reconfigurable architecture for mesh-arrays with PE and link faults, IEICE Trans. Inf. and Syst. E80-D(9) (1997), 879-885. [4] T. Horita and I. Takanami, Fault-tolerant processor arrays based on the -track switches with flexible spare distributions, IEEE Trans. Comput. 49(6) (2000), 542-552. [5] T. Horita and I. Takanami, A system for efficiently self-reconstructing -track switch torus arrays, IEICE Trans. Inf. and Syst. E84-D(12) (2001), 1801-1809. [6] T. Horita and I. Takanami, A system for efficiently self-reconstructing array system using E- -track switches, IEICE Trans. Inf. and Syst. E86-D(12) (2003), 2743-2752. [7] J. S. N. Jean, H. C. Fu and S. Y. Kung, Yield enhancement for WSI array processors using two-and-half-track switches, Proc. IEEE Int’l Conf. WSI, 1990, pp. 243-250. [8] J. H. Kim and S. M. Reddy, On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement, IEEE Trans. Comput. 38(4) (1989), 515-525. [9] G. Kim and H. Yoon, On submesh allocation for mesh multicomputers: a best-fit allocation and a virtual submesh allocation for faulty meshes, IEEE Trans. Parallel and Distributed Systems 9(2) (1998), 175-185. [10] I. Koren and A. D. Singh, Fault tolerance in VLSI circuits, IEEE Comput. 23(7) (1990), 73-83. [11] S. Y. Kung, S. N. Jean and C. W. Chang, Fault-tolerant array processors using single-track switches, IEEE Trans. Comput. 38(4) (1989), 501-514. [12] L. E. LaForge, What designers of microelectronic systems should know about arrays spared by rows and columns, IEEE Trans. Reliability 49(3) (2000), 251-272. [13] C. W. H. Lam, H. F. Li and R. Jakakumar, A study of two approaches for reconfiguring fault-tolerant systolic arrays, IEEE Trans. Comput. 38(6) (1989), 833-844. [14] C. P. Low, An efficient reconfiguration algorithm for degradable VLSI/WSI arrays, IEEE Trans. Comput. 49(6) (2000), 553-559. [15] C. P. Low and H. W. Leong, On the reconfiguration of degradable VLSI/WSI arrays, IEEE Trans. Computer-Aided Design. 16(10) (1997), 1213-1221. [16] T. E. Mangir and A. Avizienis, Fault-tolerant design for VLSI: Effect of interconnection requirements on yield improvement of VLSI designs, IEEE Trans. on Computer C-31(7) (1982), 609-615. [17] B. M. Maziarz and V. K. Jain, Automatic reconfiguration and yield of the TESH multicomputer network, IEEE Trans. Comput. 51(8) (2002), 963-972. [18] R. Negrini, M. G. Sami and R. Stefanelli, Fault-tolerance through reconfiguration of VLSI and WSI arrays, MIT Press Series in Computer Systems, MIT Press, 1989. [19] I. Numata and S. Horiguchi, Efficient reconfiguration scheme for meshconnected network: The recursive shift approach, Proc. IEEE Int’l Symp. on Parallel Architectures, Algorithms and Networks, June 1996, pp. 221-227. [20] A. L. Rosenberg, The diogenes approach to testable fault-tolerant arrays of processors, IEEE Trans. Comput. C-32(10) (1983), 902-910. [21] V. P. Roychowdhury, J. Bruck and T. Kailath, Efficient algorithms for reconstruction in VLSI/WSI array, IEEE Trans. Comput. 39(4) (1989), 480-489. [22] M. Sami and R. Stefanelli, Reconfigurable architectures for VLSI processing arrays, Proc. IEEE, 1986, pp. 712-722. [23] N. Shigei and H. Miyajima, On the search for effective spare arrangement for reconfigurable processor arrays using genetic algorithm, IEICE Trans. Fundamentals E81-A(9) (1998), 1898-1901. [24] N. Shigei, H. Miyajima and S. Murashima, On efficient spare arrangements and an algorithm with relocating spares for reconfiguring processor arrays, IEICE Trans. Fundamentals E80-A(6) (1997), 988-995. [25] A. D. Singh, Interstitial redundancy: An area efficient fault tolerance scheme for large area VLSI processor arrays, IEEE Trans. Comput. 37(11) (1988), 1398-1410. [26] M. D. Smith and P. Mazumder, Generation of minimal vertex covers for row/column allocation in self-repairable arrays, IEEE Trans. Comput. 45(1) (1996), 109-115. [27] I. Takanami, K. Kurata and T. Watanabe, A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches, Proc. Int’l Conf. on WSI, 1995, pp. 101-110. [28] T. A. Varvarigou, V. P. Roychowdhury and T. Kailath, A polynomial time algorithm for reconfiguring multiple-track models, IEEE Trans. Comput. 42(4) (1993), 385-395. [29] T. Yamada and S. Ueno, Fault-tolerant meshes with efficient layouts, IEICE Trans. Inf. and Syst. E81-D(1) (1998), 56-65. [30] L. Zhang, Fault-tolerant meshes with small degree, IEEE Trans. Comput. 51(5) (2002), 553-560.

Keywords and phrases: mesh-connected processor arrays, run-time fault-tolerance, reconfiguration, 1.5-track switches, E-1.5-track switches.

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