Far East Journal of Experimental and Theoretical Artificial Intelligence
Volume 5, Issue 1-2, Pages 27 - 44
(May 2010)
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AN ASIC IMPLEMENTATION FOR TESTING OF A LADDER DIAGRAM USING A BOOLEAN PETRI NET
Jui-I Tsai, Bao-Tung Lin and Ching-Cheng Teng
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Abstract:
This paper proposes a method for testing and troubleshooting a ladder diagram (LD). This approach first introduces the concept of integrated circuit testing to describe a basic LD and constructs a fault-free model of a Boolean Petri net (BPN). The BPN can directly generate test events of the LD from the transition sequence of the BPN. The BPN can be represented graphically, which provides a quick and direct way to convert LDs to hardware description languages (HDLs) for fault-free circuit based application-specific integrated circuits (ASICs). The response comparison of a fault-free circuit (i.e., ASIC circuit) and a fault circuit (i.e., LD circuit) can detect fault occurrence to aid in troubleshooting. Finally, examples demonstrate the usefulness of this approach. |
| Keywords and phrases: Petri net, Boolean Petri net, logic diagram, PLC, HDL, ASIC, fault- free model. |
| Communicated by Shun-Feng Su |
| Number of Downloads: 156 | Number of Views: 673 |
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