Far East Journal of Electronics and Communications
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Abstract: The present study evaluates four designs of XOR using
our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL)
circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation,
is used for a -bit array 2PASCL multiplier. Based on simulation
results obtained using 0.18-mm standard CMOS technology, at transition frequencies
of 1 to 100 MHz, the -bit array 2PASCL multiplier exhibits a maximum power
dissipation that is 55% lower
than that of a static CMOS. These results indicate that 2PASCL technology can be
advantageous when applied to low-power digital devices operated at low
frequencies, such as radio-frequency identification (RFID) tags, smart cards,
and sensors.
Keywords and phrases: low-power, adiabatic logic circuit, power supply clock, power dissipation, adiabatic XOR logic design.
