Abstract: This paper deals with redundant 2D mesh and torus processor arrays using 1.5-track switches, considering faults of switching networks together with processor faults. Variants of the arrays are defined based on the types of distributions of spare processors and the types of switching networks, and some of them have the same processor redundancies as each other but the fabrication-time costs are different. We analyze in detail by
simulation, how the reliability of a total system changes according to the
reliabilities of switching networks as well as that of a processor and show the
concrete values of and when
the reliability of the array is almost the same even if its variant is changed,
and when it is not so, respectively, where and are the ratio of the hardware complexities of a track
to a processor, and that of a contact point of a switch to a processor,
respectively. From the analysis, the results which must be an effective basis
for the design offault-tolerant 2D
processor arrays using 1.5-TSs are shown.
Keywords and phrases: 2D mesh- or torus-connected processor arrays, 1.5-track switches, reconfiguration, fault tolerance, redundancy.
